Motor Voltage (VM)

8-40V

8-60V

Size

800 x 600mil / 20.32 x 15.24mm

1000 x 600mil / 25.4 x 15.24mm

MOSFET

4x WSD4066 （17mΩ）

4x DMT6018 (17 mΩ)

Heatsink

238.6 W/(m·K)铝散热片

393.6 W/(m·K)纯铜散热片

Motor Phase Current max

3.0A (rms) / 4.2A (peak)

Rs

0.075Ω

Default Mode

SPI Mode，Standalone mode selectable via solder option

PCB layer

6层，TG155

Pinout

DIAG0 & Encoder Interface pinout

Native Microsteps

up to 1/256

microPlyer Microsteps

1/256

Logic Voltage (VIO)

3-5V

Internal V-Regulator

enabled

stealthChop (quiet)

yes

spreadCycle

yes

coolStep

yes

stallGuard

yes

dcStep

yes

Power Supply

GND

Ground

VM

Motor Supply Voltage, Provide filtering capacity near pin with short loop to GND plane. Must be tied to the positive bridge supply voltage.

VIO

3.3V to 5V IO supply voltage for all digital pins.

Motor Outputs

B1

Motor Coil 1

B2

Motor Coil 1

A1

Motor Coil 2

A2

Motor Coil 2

Control Inputs

REFL_STEP

STEP input when (SD_MODE=1).or left reference input (for internal ramp generator)

REFR_DIR

DIR input (SD_MODE=1).or right reference input (for internal ramp generator)

TMC5160

EN

Enable Motor inputs: GND=on, VIO=off

CLK

CLK input. Tie to GND using short wire for internal clock or supply external clock. Internal clock-fail over circuit protects against loss of external clock signal.

SDI_CFG1

SPI data input (SPI_MODE=1) or Configuration input (SPI_MODE=0) or Next address input (NAI) for single wire interface.

SCK_CFG2

SPI serial clock input (SPI_MODE=1) or Configuration input (SPI_MODE=0)

CSN_CFG3

SPI chip select input (negative active) (SPI_MODE=1) or Configuration input (SPI_MODE=0)

SDO_CFG0

SPI data output (tristate) (SPI_MODE=1) or Configuration input (SPI_MODE=0) or Next address output (NAO) for single wire interface.

DIAG0

Diagnostics output DIAG0. Interrupt or STEP output for motion controller (SD_MODE=0, SPI_MODE=1). Use external pullup resistor with 47k or less in open drain mode. Single wire I/O (negative) (only with SD_MODE=0 and SPI_MODE=0)

ENC-BENCB_DCEN_ CFG4

Encoder B-channel input (when using internal ramp generator) or dcStep enable input (SD_MODE=1, SPI_MODE=1) – leave open or tie to GND for normal operation in this mode (no dcStep). Configuration input (SPI_MODE=0)

ENC-AENCA_DCIN_ CFG5

Encoder A-channel input (when using internal ramp generator) or dcStep gating input for axis synchronization (SD_MODE=1, SPI_MODE=1) or Configuration input (SPI_MODE=0)

ENC-NENCN_DCO_ CFG6

Encoder N-channel input (SD_MODE=0) or dcStep ready output (SD_MODE=1). With SD_MODE=0, pull to GND or VCC_IO, if the pin is not used for an encoder.

0

1

**Standalone Mode，Step-DIR Interface，CFG pins config：**Default Mode，SPI Mode，Step-DIR Interface：The STEP/DIR inputs control the driver the chip is in standalone mode and pins have their CFG functions.

0

0

The internal ramp generator generates step pulses，enable UART operation（but the DIAG1_SWP doesn't pinout，can't use the UART interface）

1

1

**（Default）SPI Mode，Step-DIR Interface：**The STEP/DIR inputs control the driver the SPI interface is enabled. Integrated pull down resistor.

1

0

The internal ramp generator generates step pulses， the SPI interface is enabled.